1. Field
An embodiment of the present invention relates to the field of analysis of defects in integrated circuits and, more particularly, to extracting likely bridge sites.
2. Discussion of Related Art
A component of defect analysis is a process used to identify areas of an integrated circuit that are more likely to be adversely affected by a manufacturing defect. The output of this process is used to design manufacturing tests targeted at detecting failures that may result from such defects.
A list of bridges, for example, may be identified during defect analysis. A bridge occurs due to a point defect that extends across two or more conductive lines or nets to cause an electrical short between them.
The likelihood of occurrence of a particular bridge may be measured by its weighted critical area (WCA). The critical area for a two net bridge for a given defect size, as the term is used herein, is the area over which the center of the defect can lie and cause the two nets to bridge. The WCA of two nets is defined as the sum of the critical areas for a particular defect size weighted by the probability of occurrence of that defect size.
Carafe, developed at the University of California, Santa Cruz, is an example of such a tool that may be used to extract potential bridges. For each layer and each adjacent layer pair in a flattened layout of an integrated circuit, Carafe generates fault primitives referred to as xe2x80x9clength-widths.xe2x80x9d Then, for each defect size to be analyzed, Carafe calculates corresponding critical areas from each of the length-widths. These critical areas are merged or intersected for an entire layer or layer pair to produce the critical area contribution of two-net bridges for the layer or layer pair for the particular defect size. The critical areas for each layer and layer pair for that defect size are then added together to find the overall critical area for the defect size. This overall critical area is then weighted with corresponding defect data to produce the WCA for the defect size. The above-described method is repeated for each defect size.
LOBS is another example of a prior fault extraction tool. LOBS uses a sliding window algorithm to identify critical areas. LOBS places a xe2x80x9cwindowxe2x80x9d at one corner of a flattened layout in a layer or layer pair. A small set of rules is then used to calculate the critical area contributions from the region of the layout within the window. The window is then shifted to an adjacent area and the process is repeated until the entire layout has been covered.
Both Carafe and LOBS rely on a flattened version of a layout (i.e. a layout that is represented geometrically), wherein the features are annotated with the names of the nets to which they belong. This limits the size of circuits that can be handled due to memory constraints. For some of today""s integrated circuits, for example, it may not be possible to produce a flattened layout representing an entire chip and/or a flattened layout may be so large that it may not be possible with current tools to calculate weighted critical areas.
CREST, developed at Carnegie Mellon University, is another example of a prior fault extraction tool. CREST calculates the WCA of bridges from a hierarchical layout description. By using a hierarchical layout description instead of a flattened layout as used by Carafe, CREST may potentially be able to handle larger layout databases. In doing so, however, CREST may sacrifice accuracy in computing WCA values and may fail to identify important bridges that could be identified using the flattened layout. CREST may also compromise accuracy of WCA calculations by assuming that the layout does not contain xe2x80x9cover the cellxe2x80x9d or xe2x80x9cthrough the cellxe2x80x9d routing. Further, CREST does not provide for layouts in which features are only partially labeled and/or some features may have multiple names depending on which area of the chip the feature is traversing.
Thus, the particular extraction tool used to identify likely bridges can have a significant impact on the accuracy and efficiency of the fault extraction process. Inaccurate fault extraction may compromise the quality of integrated circuit tests developed based on the output of the fault extraction. Inefficient fault extraction may take an excessive amount of time such that it is not feasible to completely analyze larger, more complex circuits.
As integrated circuits continue to increase in complexity, fault extraction using prior fault extraction tools may become increasingly difficult.